Impact of Input Encoding and ADC Resolution on Matrix-Vector Multiplication Accuracy
Author:
Affiliation:
1. University of Pavia,Department of Electrical, Computer, and Biomedical Engineering,Italy
2. ST Microelectronics,Agrate Brianza,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10559643/10559661/10559732.pdf?arnumber=10559732
Reference5 articles.
1. 16.7 A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications
2. 16.5 DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching
3. 34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices
4. HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
5. Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format
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