CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference-Reference-Cited by-同舟云学术

CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

Published:2022-04 Issue:4 Volume:57 Page:1013-1026
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Prabhu Kartik¹^ORCID,Gural Albert¹,Khan Zainab F.¹,Radway Robert M.¹,Giordano Massimo¹^ORCID,Koul Kalhan¹,Doshi Rohan¹,Kustin John W.¹^ORCID,Liu Timothy¹,Lopes Gregorio B.¹,Turbiner Victor¹,Khwa Win-San²,Chih Yu-Der²,Chang Meng-Fan²,Lallement Guenole³^ORCID,Murmann Boris¹^ORCID,Mitra Subhasish¹^ORCID,Raina Priyanka¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

2. Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan

3. Reality Labs, Meta Platforms, Inc, Sunnyvale, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/4/9741814/9690772-aam.pdf

Reference67 articles.

1. A high-performance low-power highly manufacturable embedded DRAM technology using backend hi-$k$ MIM capacitor at 40 nm node and beyond;chen;Proc Int Symp VLSI Technol Syst Appl,2011

2. A 40 nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140 MHz read speed and data memory with 1M cycles endurance;yu;Proc Symp VLSI Circuits,2017

3. 7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation

4. Illusion of large on-chip memory by networked computing chips for neural network inference

5. CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

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