Low-power FinFET circuit synthesis using surface orientation optimization
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5450668/5456897/05457187.pdf?arnumber=5457187
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node;Australian Journal of Electrical and Electronics Engineering;2022-04-26
2. Dual-Port 8T SRAM Cell Design with Shorted Gate FinFET for Leakage Reduction and Improved Stability;Intelligent Computing Techniques for Smart Energy Systems;2022
3. Noise Voltage: A New Dependability Concern in Low-Power FinFET-Based Priority Encoder at 45 nm Technology;Smart Trends in Computing and Communications: Proceedings of SmartCom 2020;2020-07-18
4. Integrating flipped drain and power gating techniques for efficient FinFET logic circuits;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2018-04-19
5. Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits;Journal of Computational Electronics;2017-07-24
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