SAPON approach: A new technique for Low Power VLSI Design-Reference-Cited by-同舟云学术

SAPON approach: A new technique for Low Power VLSI Design

Published:2021-11-26 Issue: Volume: Page:
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Container-title:2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC)
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Author:

Arumugam N¹,Shakthi Priya M²,Subramanian Suntrakanesh³

Affiliation:

1. Government College of Technology,Department of Computer Science Engineering,Coimbatore,India

2. Government College of Technology,Department of ECE,Coimbatore,India

3. Government College of Technology,Department of EIE,Coimbatore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9708066/9708067/09708489.pdf?arnumber=9708489

Reference13 articles.

1. Dynamic power reduction techniques for CMOS logics using 45nm technology;yadav;International Conference on Intelligent Computing and Smart Communication 2019,2019

2. Design and Simulation of Reliable Low Power CMOS Logic Gates

3. A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology;maryan;Circuits Systems and Signal Processing,2021

4. LECTOR: a technique for leakage reduction in CMOS circuits

5. LCNT-an approach to minimize leakage power in CMOS integrated circuits

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