IC stacking technology using fine pitch, nanoscale through silicon vias-Reference-Cited by-同舟云学术

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IC stacking technology using fine pitch, nanoscale through silicon vias

Published: Issue: Volume: Page:
ISSN:
Container-title:53rd Electronic Components and Technology Conference, 2003. Proceedings.
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Author:

Spiesshoefer S.,Schaper L.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8632/27358/01216347.pdf?arnumber=1216347

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. 3D-DNaPE: Dynamic Neighbor-Aware Performance Enhancement for Thermally Constrained 3D Many-Core Systems;IEEE Access;2023

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4. Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI);Electronics;2022-01-12

5. Assessment of through‐silicon‐vias with different configurations of ground vias and accounting for substrate losses;International Journal of RF and Microwave Computer-Aided Engineering;2021-07-17

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