On automatic testpoint insertion in sequential circuits-Reference-Cited by-同舟云学术

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On automatic testpoint insertion in sequential circuits

Published: Issue: Volume: Page:
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Container-title:Proceedings. International Test Conference 1990
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Author:

Gundlach H.H.S.,Muller-Glaser K.-D.

Publisher

IEEE Comput. Soc. Press

Link

http://xplorestaging.ieee.org/ielx5/485/3370/00114132.pdf?arnumber=114132

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Hybrid Test Point Insertion Strategy for Improved Test Metrics;2024 IEEE 8th International Test Conference India (ITC India);2024-07-21

2. Nonscan design for testability for synchronous sequential circuits based on conflict resolution;IEEE Transactions on Computers;2003-08

3. Test-point insertion: scan paths through functional logic;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1998

4. Testability-based partial scan analysis;Journal of Electronic Testing;1995

5. Partial scan flip-flop selection by use of empirical testability;Journal of Electronic Testing;1995

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