Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices-Reference-Cited by-同舟云学术

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Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

Published:2014-06 Issue:6 Volume:61 Page:2064-2070
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Hsiao Yi-Hsuan,Lue Hang-Ting,Chen Wei-Chen,Chang Kuo-Pin,Shih Yen-Hao,Tsui Bing-Yue,Hsieh Kuang-Yeu,Lu Chih-Yuan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/6817621/06813697.pdf?arnumber=6813697

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