Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC-Reference-Cited by-同舟云学术

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Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC

Published:2021-10-06 Issue: Volume: Page:
ISSN:
Container-title:2021 18th International SoC Design Conference (ISOCC)
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Author:

Han Donghyun,Lee Youngkwang,Lee Sooryeong,Kang Sungho

Funder

Samsung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9613844/9613845/09613959.pdf?arnumber=9613959

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 2D/2.5D/3D Heterogeneous Integration;Electronic Device Failure Analysis Technology Roadmap;2023-11-01

2. 2D/2.5D/3D Heterogeneous Integration;Electronic Device Failure Analysis Technology Roadmap;2023-11-01

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