Formal derivation of a systolic array for recursive least squares estimation-Reference-Cited by-同舟云学术

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Formal derivation of a systolic array for recursive least squares estimation

Published:1996-03 Issue:3 Volume:43 Page:247-254
ISSN:1057-7130
Container-title:IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Proudler I.K.,McWhirter J.G.,Moonen M.,Hekstra G.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Link

http://xplorestaging.ieee.org/ielx4/82/10403/00486470.pdf?arnumber=486470

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3. Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm;The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology;2007-01-09

4. FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder;IEEE Transactions on Circuits and Systems I: Regular Papers;2005-02

5. An improved stochastic gradient algorithm for principal component analysis and subspace tracking;IEEE Transactions on Signal Processing;1997

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