3-Layer Stacking Technology with Pixel-Wise Interconnections for Image Sensors Using Hybrid Bonding of Silicon-on-Insulator Wafers Mediated by Thin Si Layers-Reference-Cited by-同舟云学术

3-Layer Stacking Technology with Pixel-Wise Interconnections for Image Sensors Using Hybrid Bonding of Silicon-on-Insulator Wafers Mediated by Thin Si Layers

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

Goto Masahide¹,Honda Yuki¹,Nanba Masakazu¹,Iguchi Yoshinori¹,Higurashi Eiji²,Saraya Takuya³,Kobayashi Masaharu³,Toshiyoshi Hiroshi³,Hiramoto Toshiro³

Affiliation:

1. NHK Science & Technology Research Laboratories,Tokyo,Japan

2. National Institute of Advanced Industrial Science and Technology,Ibaraki,Japan

3. The University of Tokyo; Tokyo, Japan,Tokyo,Japan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816403.pdf?arnumber=9816403

Reference11 articles.

1. Three-dimensional integrated CMOS image sensors with pixel-parallel A/D converters fabricated by direct bonding of SOI layers

2. 4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM

3. Cu/SiO2 hybrid bonding obtained by surface-activated bonding method at room temperature using Si ultrathin films

4. A wide-dynamic-range, low-power photosensor array

5. Development of Novel MOSFET with Front and Back Side Electrodes for 3D-Structured Image Sensors

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