Physical Insights of Si-Core-SiGe-Shell Gate-All-Around Nanosheet pFET for 3 nm Technology Node
Author:
Affiliation:
1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
Funder
NSFC
MOST
International Partnership Program of Chinese Academy of Sciences
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10136238/10112642.pdf?arnumber=10112642
Reference39 articles.
1. A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
2. Quantum size effect in core-shell structured silicon-germanium nanowires
3. Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around NSFET for 5 nm Technology Node
4. SiGe nanowires: Structural stability, quantum confinement, and electronic properties
5. Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel
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4. Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond;IEEE Transactions on Electron Devices;2024-03
5. Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm;IEEE Transactions on Electron Devices;2023-12
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