A Device-Circuit Aging Simulation Framework Integrating Trap-Based Models and Sensitivity Analysis for FinFET Technology-Reference-Cited by-同舟云学术

A Device-Circuit Aging Simulation Framework Integrating Trap-Based Models and Sensitivity Analysis for FinFET Technology

Published:2024-01 Issue:1 Volume:71 Page:206-212
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Li Yu¹^ORCID,Xue Yongkang²^ORCID,Sun Zixuan³^ORCID,Shen Cong¹,Ren Pengpeng²^ORCID,Ji Zhigang²^ORCID,Zhang Lining¹^ORCID,Wang Runsheng³^ORCID,Huang Ru³

Affiliation:

1. School of Electronic and Computer Engineering, Peking University, Shenzhen, China

2. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiaotong University, Shanghai, China

3. School of Integrated Circuits, Peking University, Beijing, China

Funder

Natural Science Foundation of China

Shenzhen Science and Technology Project

Higher Education Discipline Innovation Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10382412/10286429.pdf?arnumber=10286429

Reference24 articles.

1. Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process

2. Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?

3. Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator

4. Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis

5. Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

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