A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation-Reference-Cited by-同舟云学术

A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

Published:2024-01 Issue:1 Volume:71 Page:453-460
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Andavarapu Rakesh¹^ORCID,Bagati Susmitha¹^ORCID,Valasa Sresta²^ORCID,Kotha Venkata Ramakrishna²^ORCID,Bhukya Sunitha²,Padhi Santosh Kumar²^ORCID,Vadthiya Narendar²^ORCID

Affiliation:

1. Department of ECE, MVGR College of Engineering, Vizianagaram, India

2. Department of Electronics and Communication Engineering, National Institute of Technology Warangal, Warangal, India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10382412/10352097.pdf?arnumber=10352097

Reference35 articles.

1. Gate length scaling and threshold voltage control of double-gate MOSFETs

2. Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

3. Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

4. FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

5. Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

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1. Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level;Microelectronics Reliability;2024-09

2. Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance;ECS Journal of Solid State Science and Technology;2024-07-01

3. Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications;ACS Applied Electronic Materials;2024-05-09

4. A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis;Microelectronics Journal;2024-04