A 25% Duty -Cycle Clock Generation Circuit in 0.13 μ m CMOS-Reference-Cited by-同舟云学术

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A 25% Duty -Cycle Clock Generation Circuit in 0.13 μ m CMOS

Published:2022-10-28 Issue: Volume: Page:
ISSN:
Container-title:2022 7th International Conference on Integrated Circuits and Microsystems (ICICM)
language:
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Author:

Xu Minli¹,Zhang Youming¹,Tang Xusheng¹,Li Junjie²,Huang Fengyi¹

Affiliation:

1. Southeast University,School of Microelctronics,Nanjing,China,210096

2. Southeast University,School of Information Science and Engineering,Nanjing,China,210096

Funder

Research and Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011355.pdf?arnumber=10011355

Reference13 articles.

1. A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback

2. A Gain Boosted N-Path Filter with Improved Out of Band Rejection

3. Widely Tunable 4th Order Switched G$_m$-C Band-Pass Filter Based on N-Path Filters

4. Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation

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