A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration-Reference-Cited by-同舟云学术

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A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

Published:2022-08 Issue:5 Volume:32 Page:1-12
ISSN:1051-8223
Container-title:IEEE Transactions on Applied Superconductivity
language:
Short-container-title:IEEE Trans. Appl. Supercond.

Author:

Wang Ching-Cheng¹,Mak Wai-Kei¹^ORCID

Affiliation:

1. Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan

Funder

Ministry of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/77/9741394/09745333.pdf?arnumber=9745333

Reference20 articles.

1. FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model

2. SimPL: An Effective Placement Algorithm

3. Ripple: An effective routability-driven placer by iterative cell movement

4. POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints

5. Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model

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