Duration of the High Breakdown Voltage Phase in Deep Depletion SOI LDMOS-Reference-Cited by-同舟云学术

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Duration of the High Breakdown Voltage Phase in Deep Depletion SOI LDMOS

Published:2007-08 Issue:8 Volume:28 Page:753-755
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Napoli E.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/4278348/04278371.pdf?arnumber=4278371

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Ultra-Low Specific On-Resistance LDMOS With Segmented LOCOS In 0.18 μm BCD Process Platform;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

2. Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer;Micromachines;2023-04-20

3. Analysis of Deep Depletion Effect in SOI LDMOS Substrate with Numerical Simulation;2022 4th Asia Energy and Electrical Engineering Symposium (AEEES);2022-03-25

4. Improve the Dynamic Breakdown Voltage of SOI LDMOS Devices by Eliminating the Effect of Deep Depletion in Substrate;2021 3rd Asia Energy and Electrical Engineering Symposium (AEEES);2021-03-26

5. Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage;IEEE Access;2020

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