A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/4/4787550/04787551.pdf?arnumber=4787551
Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Frontend Sampling Networks;Synthesis Lectures on Engineering, Science, and Technology;2023
2. A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-05
3. A 34.3 dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector;Analog Integrated Circuits and Signal Processing;2021-03-09
4. A study of analog decision feedback equalization for ADC-Based serial link receivers;Integration;2019-01
5. A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS;AEU - International Journal of Electronics and Communications;2018-05
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