DDR5 Electrical Challenges in High-Speed Server Design
Author:
Affiliation:
1. Dell Technologies Server Group,Round Rock,TX,USA
2. Dell Technologies Server Group,Bangalore,India
3. Dell Technologies Server Group,Taipei,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10217221/10217352/10217517.pdf?arnumber=10217517
Reference8 articles.
1. Signal Integrity Characterization of Via Stubs on High Speed DDR4 Channels;dannan;DesignCon,2020
2. Equation-Based Solutions to Coupled, Asymmetrical, Lossy, and Nonuniform Microstrip Lines for Tab-Routing Applications
3. DDR5 Design Challenges;bhagwath;IEEE Workshop on Signal and Power Integrity,2018
4. A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx
5. Maximizing DDR5 Eye-Opening by Identifying Buffer Settings Using Optimization Algorithms;bhagwath;DesignCon,2020
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1. An Energy Efficient DDR5 I/O Performance Boost in Clamshell Configuration by Charge Pumping From Non-Target Device;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
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