Simulation-Based Study of Gaussian-Doped Channel in Stacked Gate Oxide MOS Transistor
Author:
Affiliation:
1. Engineering Jaypee Institute of Information Technology,Department of Electronics and Communication,Noida,India
2. Jaypee Institute of Information Technology,Department of Electronics and Communication Engineering,Noida,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10440964/10440724/10441117.pdf?arnumber=10441117
Reference16 articles.
1. Ion Implanted MOSFET's With Very Short Channel Lengths
2. Chip Power-Frequency Scaling in 10/7nm Node
3. A comprehensive approach to the design and fabrication of a field-effect transistor with graphene channel
4. Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
5. A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs
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