An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators
Author:
Affiliation:
1. Infineon Technologies Austria, Villach, Austria
2. Institute of Microelectronics, University of Ulm, Ulm, Germany
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10083009/09964091.pdf?arnumber=9964091
Reference9 articles.
1. A noise coupled ? ? architecture using a non uniform quantizer;torreño;Proc NORCAS,2015
2. A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator
3. A 20 MHz bandwidth continuous-time delta-sigma ADC achieving 82.1 dB SNDR and 100 dB SFDR using a time-interleaved virtual-ground-switched FIR feedback DAC;baluni;Proc CICC,2020
4. Improved ? ? DAC linearity using data weighted averaging;baird;Proc ISCAS,1995
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth;IEEE Journal of Solid-State Circuits;2024
2. Oversampling ADC: A Review of Recent Design Trends;IEEE Access;2024
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