A CMOS Complementary Common Gate Capacitive Cross-Coupled Frequency Doubler
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea
Funder
Samsung Electronics
National Research Foundation of Korea (NRF) Grant
Korea Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9869776/09775123.pdf?arnumber=9775123
Reference21 articles.
1. A 60 GHz CMOS-SOI Stacked Push-Push Frequency Doubler with 12 dBm Output Power and 20% Efficiency
2. A Buffer-Less Wideband Frequency Doubler in 45-nm CMOS-SOI With Transistor Multiport Waveform Shaping Achieving 25% Drain Efficiency and 46–89 GHz Instantaneous Bandwidth
3. A Truly Balanced Q-Band CMOS Frequency Doubler Based on Hybrid Quadrature Coupler
4. An IR-UWB CMOS Transceiver for High-Data-Rate, Low-Power, and Short-Range Communication
5. CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices
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3. A 52–65 GHz Frequency Quadrupler With Low Conversion Loss and High Harmonic Rejection Ratio in 28-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08
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