A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA-Reference-Cited by-同舟云学术

A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA

Published:2022-12 Issue:12 Volume:69 Page:5089-5093
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Zhang Jian¹^ORCID,Wang Ran¹,Wang Tengbo²,Liu Jia³,Dang Shibo¹,Zhang Guohe¹^ORCID

Affiliation:

1. School of Microelectronics and the Key Laboratory of Micro-Nano Electronics and System Integration of Xi’an City, Xi’an Jiaotong University, Xi’an, China

2. School of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, China

3. No. 24 Institute, China Electronics Technology Group Corporation, Chongqing, China

Funder

the Basic Research of Natural Science in Shaanxi Province

the Strengthening Basic Disciplines Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9969381/09858074.pdf?arnumber=9858074

Reference20 articles.

1. Loihi: A Neuromorphic Manycore Processor with On-Chip Learning

2. An FPGA Implementation of Deep Spiking Neural Networks for Low-Power and Fast Classification

3. A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps

4. Bio-inspired digit recognition using reward-modulated spike-timing-dependent plasticity in deep convolutional networks

5. STDP-based spiking deep convolutional neural networks for object recognition

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