Author:
Sarangi Smruti R.,Kalayappan Rajshekar,Kallurkar Prathmesh,Goel Seep,Peter Eldhose
Cited by
31 articles.
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1. CASH: Criticality-Aware Split Hybrid L1 Data Cache;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. SEFsim: A Statistically-Guided Fast DRAM Simulator;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05
3. EMAClave: An Efficient Memory Authentication for RISCV Enclaves;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. JASS: A Tunable Checkpointing System for NVM-Based Systems;2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC);2023-12-18
5. Enhancing Microarchitecture Performance through Synergistic Dynamic Branch Prediction and Cache Prefetching;2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom);2023-12-07