A quantitative methodology for rapid prototyping and high-level synthesis of signal processing algorithms
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx4/78/7823/00330377.pdf?arnumber=330377
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Designs based on Finite State Machines;Digital Design of Signal Processing Systems;2011-01-31
2. VERIFICATION OF DATAFLOW SCHEDULING;International Journal of Software Engineering and Knowledge Engineering;2008-09
3. Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs;2008 IEEE International Symposium on Circuits and Systems;2008-05
4. Verification method of dataflow algorithms in high-level synthesis;Journal of Systems and Software;2007-08
5. Overlapped Scheduling Techniques for High-Level Synthesis and Multiprocessor Realizations of DSP Algorithms;Advanced Techniques for Embedded Systems Design and Test;1998
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