Low Power Neural Network by Reducing SRAM Operating Voltage
Author:
Affiliation:
1. Graduate School of Science and Engineering, Chiba University, Chiba, Japan
2. Graduate School of Engineering, Chiba University, Chiba, Japan
Funder
Japan Society for the Promotion of Science (JSPS) KAKENHI
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09936634.pdf?arnumber=9936634
Reference15 articles.
1. An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
2. Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks
3. Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor
4. SRAM voltage scaling for energy-efficient convolutional neural networks
5. Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network
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