Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances-Reference-Cited by-同舟云学术

Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

Published:2021 Issue: Volume:9 Page:50281-50290
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Lee Sang Ho^ORCID,Jang Won Douk^ORCID,Yoon Young Jun,Seo Jae Hwa,Mun Hye Jin^ORCID,Cho Min Su^ORCID,Jang Jaewon^ORCID,Bae Jin-Hyuk^ORCID,Kang In Man^ORCID

Funder

National Research Foundation of Korea (NRF) grant funded by the Korea Government [Ministry of Science and ICT (MSIT)]

BK21 FOUR project funded by the Ministry of Education, South Korea

Ministry of Trade, Industry and Energy

Korea Semiconductor Research Consortium (KSRC) Support Program for developing the future semiconductor devices

NRF grant funded by the Korean Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/9312710/09387306.pdf?arnumber=9387306

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1. Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking;Silicon;2024-08-27

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3. Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations;Japanese Journal of Applied Physics;2024-02-21

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5. Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries;Nanomaterials;2023-07-07