Performance Evaluation of High-κ Dielectric Ferro-Spacer Engineered Si/SiGe Hetero-Junction Line TFETs: A TCAD Approach
Author:
Affiliation:
1. Department of Electronics Engineering, VLSI Design Group, Sardar Vallabhbhai National Institute of Technology, Gujarat, Surat, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/94/10142149/10098817.pdf?arnumber=10098817
Reference35 articles.
1. Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight
2. Tunneling Field-Effect Transistor: Capacitance Components and Modeling
3. ${\rm Si}_{\rm x}{\rm Ge}_{1\hbox{-}{\rm x}}$ Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement
4. On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors
5. Investigation on the Effects of Gate-Source Overlap/Underlap and Source Doping Gradient of n-Type Si Cylindrical Gate-All-Around Tunnel Field-Effect Transistors
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