Novel In-Situ AlN/p-GaN Gate HEMTs With Threshold Voltage of 3.9 V and Maximum Applicable Gate Voltage of 12.1 V-Reference-Cited by-同舟云学术

Novel In-Situ AlN/p-GaN Gate HEMTs With Threshold Voltage of 3.9 V and Maximum Applicable Gate Voltage of 12.1 V

Published:2023-02 Issue:2 Volume:70 Page:424-428
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Wu Yinhe¹^ORCID,Liu Shuang²^ORCID,Zhang Jincheng¹^ORCID,Zhao Shenglei¹^ORCID,Li Xiangdong³,Zhang Kai⁴,Ai Yue¹,Zhang Weihang⁵^ORCID,Chen Tangsheng⁴,Hao Yue¹^ORCID

Affiliation:

1. Key Laboratory of Wide Band Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an, China

2. Key Laboratory of Wide Band Gap Semiconductor Materials and Devices, Xidian University, Xi’an, China

3. Guangzhou Wide Bandgap Semiconductor Innovation Center, Guangzhou Institute of Technology, Xidian University, Guangzhou, China

4. Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing, China

5. School of Microelectronics, Xidian University, Xi’an, China

Funder

National Natural Science Foundation of China

National Science Fund for Distinguished Young Scholars

National Key Research and Development Program of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10025571/10018177.pdf?arnumber=10018177

Reference28 articles.

1. Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p}$ -GaN Gate HEMTs

2. Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

3. E-Mode p-n Junction/AlGaN/GaN (PNJ) HEMTs

4. p-GaN Gate HEMT With Surface Reinforcement for Enhanced Gate Reliability

5. Normally-Off AlGaN/GaN Heterojunction Metal-Insulator-Semiconductor Field-Effect Transistors With Gate-First Process

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