Testability Considerations for Custom Processing-In-Memory Cores
Author:
Affiliation:
1. University of Limerick,Department of Electronic and Computer Engineering,Limerick,Ireland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10537606/10537804/10537816.pdf?arnumber=10537816
Reference18 articles.
1. Embedded Processor-In-Memory Architecture for Accelerating Arithmetic Operations
2. A case for intelligent RAM
3. IEC Standard Testability Method for Embedded Core-Based Integrated Circuits
4. Computational RAM: implementing processors in memory
5. HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
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