Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs-Reference-Cited by-同舟云学术

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Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Published:2007-01 Issue:1 Volume:42 Page:74-83
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kanno Yusuke,Mizuno Hiroyuki,Yasu Yoshihiko,Hirose Kenji,Shimazaki Yasuhisa,Hoshi Tadashi,Miyairi Yujiro,Ishii Toshifumi,Yamada Tetsuya,Irita Takahiro,Hattori Toshihiro,Yanagisawa Kazumasa,Irie Naohiko

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4039574/04039588.pdf?arnumber=4039588

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3. Design and energy-efficient architectures for nonvolatile static random access memory using magnetic tunnel junctions;Japanese Journal of Applied Physics;2019-03-05

4. Bespoke Processors for Applications with Ultra-low Area and Power Constraints;Proceedings of the 44th Annual International Symposium on Computer Architecture;2017-06-24

5. Enabling Effective Module-Oblivious Power Gating for Embedded Processors;2017 IEEE International Symposium on High Performance Computer Architecture (HPCA);2017-02

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