Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices-Reference-Cited by-同舟云学术

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Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices

Published:2020-08 Issue:3 Volume:66 Page:203-212
ISSN:0098-3063
Container-title:IEEE Transactions on Consumer Electronics
language:
Short-container-title:IEEE Trans. Consumer Electron.

Author:

Singhadia Ashish^ORCID,Mamillapalli Meghan,Chakrabarti Indrajit

Funder

Ministry of Electronics and Information Technology (MeitY), Government of India, through the Chip to System (C2S) Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Media Technology

Link

http://xplorestaging.ieee.org/ielx7/30/9151244/09130767.pdf?arnumber=9130767

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Memory-Centered Motion Estimation System With CTB-Based Full-Splitting Algorithm;IEEE Transactions on Consumer Electronics;2024-05

2. Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding;Lecture Notes in Computer Science;2024

3. Novel low-power pipelined DCT processor for real-time IoT applications;Journal of Real-Time Image Processing;2023-05-02

4. Extensions on Low-Complexity DCT Approximations for Larger Blocklengths Based on Minimal Angle Similarity;Journal of Signal Processing Systems;2023-03-01

5. Efficient 2D DCT architecture based on approximate compressors for image compression with HEVC intra-prediction;Journal of Real-Time Image Processing;2023-02-23

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