Load-Store Queue Sizing for Efficient Dataflow Circuits
Author:
Affiliation:
1. ETH Zurich,Department of Information Technology and Electrical Engineering,Zurich,Switzerland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9973804/9974184/09974425.pdf?arnumber=9974425
Reference33 articles.
1. SDC-based modulo scheduling for pipeline synthesis
2. Efficient methods for out-of-order load/store execution for high-performance soft processors
3. An efficient and versatile scheduling algorithm based on SDC formulation
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3. A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12
4. Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
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