A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips-Reference-Cited by-同舟云学术

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

Published:2023-03 Issue:3 Volume:58 Page:877-892
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Su Jian-Wei¹^ORCID,Chou Yen-Chi¹,Liu Ruhui¹^ORCID,Liu Ta-Wei¹,Lu Pei-Jung²,Wu Ping-Chun²,Chung Yen-Lin¹,Hong Li-Yang²,Ren Jin-Sheng¹,Pan Tianlong²,Jhang Chuan-Jia¹,Huang Wei-Hsing¹,Chien Chih-Han¹,Mei Peng-I³,Li Sih-Han³^ORCID,Sheu Shyh-Shyuan³,Chang Shih-Chieh³,Lo Wei-Chung³,Wu Chih-I³,Si Xin¹^ORCID,Lo Chung-Chuan⁴,Liu Ren-Shuo¹,Hsieh Chih-Cheng¹^ORCID,Tang Kea-Tiong¹^ORCID,Chang Meng-Fan¹^ORCID

Affiliation:

1. Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan

2. Institute of Electronic Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan

3. Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan

4. Institute of Systems Neuroscience, National Tsing Hua University (NTHU), Hsinchu, Taiwan

Funder

Industrial Technology Research Institute

Taiwan Semiconductor Research Institute

Ministry of Science and Technology (MOST)- Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10051119/09896828.pdf?arnumber=9896828

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5. A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

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