Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study
Author:
Affiliation:
1. Department of Electrical Engineering (ESAT), KU Leuven, Leuven, Belgium
2. imec, Leuven, Belgium
Funder
Ph.D. Fellowship of the Research Foundation-Flanders
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/10027614/09989418.pdf?arnumber=9989418
Reference20 articles.
1. Impact of Mixed Negative Bias Temperature Instability and Hot Carrier Stress on MOSFET Characteristics—Part II: Theory
2. Physics-based device aging modelling framework for accurate circuit reliability assessment
3. On the feasibility of spherical harmonics expansions of the Boltzmann transport equation for three-dimensional device geometries
4. Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full {V G, V D} Bias Space: Implications and Peculiarities
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1. Unveiling the Role of Interface and Dielectric Wall Traps with Self-heating Induced Aging Prediction of Forksheet FET;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03
2. A Study of the States Kinetics in NBTI and HCI Degradation based on TCAD;2023 6th International Conference on Electronics and Electrical Engineering Technology (EEET);2023-12-01
3. Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs;Micromachines;2023-07-28
4. Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03
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