A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines-Reference-Cited by-同舟云学术

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A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines

Published:2018-12 Issue: Volume: Page:
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Container-title:2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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Author:

Angeli Nico,Hofmann Klaus

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8599658/8617837/08617948.pdf?arnumber=8617948

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

2. Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element;Integration;2024-05

3. A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit;Electronics;2023-03-29

4. Programmable Delay Line With Inherent Duty Cycle Correction;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

5. Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current;Journal of Circuits, Systems and Computers;2022-06-24

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