Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders-Reference-Cited by-同舟云学术

Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders

Published:2023-02 Issue:1 Volume:40 Page:85-95
ISSN:2168-2356
Container-title:IEEE Design & Test
language:
Short-container-title:IEEE Des. Test

Author:

Subramaniyan Srinivasan¹^ORCID,Ferraz Oscar²^ORCID,Ashuthosh M. R.³,Krishna Santosh³,Wang Guohui⁴,Cavallaro Joseph R.⁴^ORCID,Silva Vitor²,Falcao Gabriel²^ORCID,Purnaprajna Madhura¹^ORCID

Affiliation:

1. Department of Computer Science and Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, India

2. Department of Electrical and Computer Engineering, Instituto de Telecomunicacoes University of Coimbra, Coimbra, Portugal

3. Department of Electronics and Communication Engineering, PES Institute of Technology Bangalore South Campus Bengaluru, Bengaluru, India

4. Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA

Funder

Funda??o para a Ci?ncia e a Tecnologia

National Science Foundation

Department of Science and Technology India

Science and Engineering Research Board

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://ieeexplore.ieee.org/ielam/6221038/10024350/9869892-aam.pdf

Reference14 articles.

1. A 630 Mbps non-binary LDPC decoder for FPGA

2. Bit Reliability-Based Decoders for Non-Binary LDPC Codes

3. FPGA implementation of nonbinary quasi-cyclic LDPC decoder based on EMS algorithm;sun;Proc Int Conf Commun Circuits Syst,2009

4. Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

5. Parallel block-layered nonbinary QC-LDPC decoding on GPU

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