Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver-Reference-Cited by-同舟云学术

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Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver

Published:2018-09 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)
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Author:

Athreya Shankarram,Hedayati Hiva,Kazemkhani Shayan,Chen Yanfei,Vats Saurabh,Scott Michael D.,Zeydel Bart,Keller Peter,Wang Jian,Avula Bhaskarareddy,Murmann Boris,Iroaga Echere

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8476980/8494227/08494254.pdf?arnumber=8494254

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique;Sensors;2024-03-15

2. Selected Issues Causing Meta-stability in Digital Circuits and Approaches to Avoiding Them;2023 21st International Conference on Emerging eLearning Technologies and Applications (ICETA);2023-10-26

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