Investigation on Underfill Properties Effect on Board Level Solder Joint Reliability for SiP Package
Author:
Affiliation:
1. Micron Semiconductor Asia Operations Pte. Ltd,Singapore,339942
2. Micron Memory Taiwan Co.,Taichung City,TA,Taiwan,42152
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10457288/10457581/10457926.pdf?arnumber=10457926
Reference11 articles.
1. Development on Fatigue Life Model of Lead-Free Solder for First Failure Prediction
2. Study on Solder Joint Shape Impact on Board Level Reliability for Managed NAND Mobile Package
3. Study on Substrate Crack through Experiment and Simulation on SSD BGA under Temperature Cycling
4. Partial Underfill Impact Study on Solder Joint Reliability in Smartphone Application
5. Analysis of edge and corner bonded PSvfBGA reliability under thermal cycling conditions by experimental and finite element methods
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