Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
Author:
Affiliation:
1. Universidade Federal do Rio Grande do Sul,PGMicro - Graduate Program on Microelectronics,Porto Alegre,RS,Brazil
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9893151/9893215/09893250.pdf?arnumber=9893250
Reference15 articles.
1. A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
2. A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier
3. A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
4. 3.5 A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques
5. 15. 5 A 0. 6V 1. 17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology;kim;2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers,2015
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