A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9152175/08824083.pdf?arnumber=8824083
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05
2. A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02
3. Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18
4. An Energy Efficient Sorting Architecture with Cell-Gating for Top-K Sorting on FPGA;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
5. Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm;Electronics;2023-05-24
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