A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM
Author:
Affiliation:
1. IIT Bombay,Department of Electrical Engineering,Mumbai,India,400076
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937479.pdf?arnumber=9937479
Reference15 articles.
1. Switching in Systems and Control
2. A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
3. A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
4. A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology
5. A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
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1. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024
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