On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators
Author:
Affiliation:
1. Universidad de Zaragoza,Department of Computer Science and Systems Engineering,Spain
2. Politecnico di Milano,Dipartimento di Elettronica, Informazione e Bioingegneria,Italy
Funder
Government of Aragon
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10456758/10456769/10456839.pdf?arnumber=10456839
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1. TensorFlow: Large-Scale Machine Learning on Heterogeneous Distributed Systems;Abadi;CoRR,2016
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3. Assessing the Effects of Low Voltage in Branch Prediction Units
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1. Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage;Microprocessors and Microsystems;2024-04
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