TCAD Study on Strain Engineering in Vertical Channel Gate-all-around Transistor-Reference-Cited by-同舟云学术

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TCAD Study on Strain Engineering in Vertical Channel Gate-all-around Transistor

Published:2023-10-24 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
language:
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Author:

Bi Ran¹,Zhang Baotong¹,Wang Jianhuan²,Zhang Jianjun³,Li Haixia¹,Li Ming¹

Affiliation:

1. Peking University,School of Integrated Circuits,Beijing,China

2. Chinese Academy of Sciences,Beijing National Laboratory for Condensed Matter Physics and Institute Physics,Beijing,China

3. Beijing Academy of Quantum Information Sciences,Beijing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396480.pdf?arnumber=10396480

Reference8 articles.

1. Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!

2. 3D integration for density and functionality;Ryckaert,2019

3. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

4. (Invited) Vertical Nanowire FET Integration and Device Aspects

5. Mapping of the mechanical response in Si/SiGe nanosheet device geometries

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance;ECS Journal of Solid State Science and Technology;2024-06-03

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