Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information

Author:

Nathamuni-Venkatesan Aparajithan1,Narayanan Ram-Venkat1,Pula Kishore1,Muthukumaran Sundarakumar1,Vemuri Ranga1

Affiliation:

1. University of Cincinnati,Digital Design Environments Lab,ECE Department,Cincinnati,Ohio,USA

Funder

National Science Foundation

Publisher

IEEE

Reference19 articles.

1. Exploring network structure, dynamics, and function using NetworkX;hagberg;Los Alamos National Lab Tech Rep,2008

2. Highway to HAL

3. Scikit-learn: Machine Learning in Python;pedregosa;Journal of Machine Learning Research,2011

4. DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

2. Reverse Engineering of RTL Controllers from Look-Up Table Netlists;2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2023-06-20

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