1. Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA;Proceedings of the 11th Latin-American Symposium on Dependable Computing;2022-11-21
2. Address-encoded byte order;Microprocessors and Microsystems;2020-10
3. Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC;2020 IEEE Latin-American Test Symposium (LATS);2020-03
4. High-Performance RISC-V Emulation;Communications in Computer and Information Science;2020
5. Fog-Assisted Translation: Towards Efficient Software Emulation on Heterogeneous IoT Devices;2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2018-05