Author:
Sadhukhan Rajat,Saha Sayandeep,Mukhopadhyay Debdeep
Cited by
5 articles.
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1. High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares;14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'24));2024-06-19
2. Security Aspects of Masking on FPGAs;2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2024-05-06
3. SRIL: Securing Registers from Information Leakage at Register Transfer Level;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
4. Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis;ACM Transactions on Embedded Computing Systems;2023-09-26
5. Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis;2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS);2022-09-12