Integrated design environment for DC/DC converter FET optimization-Reference-Cited by-同舟云学术

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Integrated design environment for DC/DC converter FET optimization

Published:1999 Issue: Volume: Page:
ISSN:
Container-title:11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)
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Author:

Sodhi R.,Brown S.,Kinzer D.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6175/16497/00764108.pdf?arnumber=764108

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Switching losses prediction methods oriented to power MOSFETs – a review;IET Power Electronics;2020-11

2. Measurement of Power Dissipation Due to Parasitic Capacitances of Power MOSFETs;IEEE Access;2020

3. Structure-based capacitance modeling and power loss analysis for the latest high-performance slant field-plate trench MOSFET;Japanese Journal of Applied Physics;2018-03-23

4. Multiphysics modeling and optimization of the driving strategy of a light duty fuel cell vehicle;International Journal of Hydrogen Energy;2017-10

5. Parasitic-Aware Design of Integrated DC–DC Converters With Spiral Inductors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-12

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