Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation
Author:
Affiliation:
1. Center for Computational Science (R-CCS),RIKEN,Japan
2. KTH Royal Institute of Technology,Sweden
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9835152/9835156/09835263.pdf?arnumber=9835263
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27
2. Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05
3. Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC;Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies;2023-06-14
4. THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC;2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2023-05
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