Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency-Reference-Cited by-同舟云学术

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Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency

Published:2016-02 Issue: Volume: Page:
ISSN:
Container-title:2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)
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Author:

Santos Paulo C.,Alves Marco A. Z.,Diener Matthias,Carro Luigi,Navaux Philippe O. A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7445296/7445297/7445363.pdf?arnumber=7445363

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cache Computing for Dew Devices at the Edge Networks;Internet of Things;2023-09-03

2. Comparison of Different Adaptable Cache Bypassing Approaches;2022 XII Brazilian Symposium on Computing Systems Engineering (SBESC);2022-11-21

3. DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks;IEEE Access;2021

4. A computation-in-memory accelerator based on resistive devices;Proceedings of the International Symposium on Memory Systems;2019-09-30

5. On the parallel programmability of JavaSymphony for multi-cores and clusters;International Journal of Ad Hoc and Ubiquitous Computing;2019

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