A 5-ns 1-Mb ECL BiCMOS SRAM-Reference-Cited by-同舟云学术

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A 5-ns 1-Mb ECL BiCMOS SRAM

Published:1990 Issue:5 Volume:25 Page:1057-1062
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Takada M.,Nakamura K.,Takeshima T.,Furuta K.,Yamazaki T.,Imai K.,Ohi S.,Sekine Y.,Minato Y.,Kimuto H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/2262/00062124.pdf?arnumber=62124

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Power Embedded BiCMOS/ECL SRAMS;Advanced Low-Power Digital Circuit Techniques;1997

2. A scalable pipelined architecture for fast buffer SRAMs;IEEE Journal of Solid-State Circuits;1996-03

3. Low-Power CMOS Random Access Memory Circuits;Low-Power Digital VLSI Design;1995

4. Low-Voltage VLSI BiCMOS Circuit Design;Low-Power Digital VLSI Design;1995

5. Total dose failures in advanced electronics from single ions;IEEE Transactions on Nuclear Science;1993-12

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